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1

I'm learning how to write makefiles and would like to create a makefile that can create multiple targets from multiple sources according to a given argument.

Here is what I tried so far:

# Compiler and others
CC=gcc

# Flags
CFLAGS = -g -c -Wall -DLOGFILE -D_REENTRANT

target1_EXEC = ../build/target1
target2_EXEC = ../build/target2

target1_SRC = ../source/target1
target2_SRC = ../source/target2

target1: TARGET=target1
target1: all

target2: TARGET=target2
target2: all

EXEC=$($(TARGET)_EXEC)
SRC=$($(TARGET)_SRC)
OBJ=$(SRC:.c=.o)

all: $(EXEC)

$(EXEC): $(OBJ)
 $(CC) $(INCLUDES) -o $@ $^ $(LDFLAGS) $(LIBS)

%.o: %.c
 $(CC) -o $@ -c $< $(CFLAGS)

I would like to call the makefile with the target as an argument:

makefile target1

But then it seems that it does not find the subtarget:

make: Nothing to be done for 'target1'.

What am I doing wrong ?

linux variables makefile

share|improve this question

asked Mar 28 at 15:07

user3923073user3923073

5166 bronze badges

add a comment
 | 

1

I'm learning how to write makefiles and would like to create a makefile that can create multiple targets from multiple sources according to a given argument.

Here is what I tried so far:

# Compiler and others
CC=gcc

# Flags
CFLAGS = -g -c -Wall -DLOGFILE -D_REENTRANT

target1_EXEC = ../build/target1
target2_EXEC = ../build/target2

target1_SRC = ../source/target1
target2_SRC = ../source/target2

target1: TARGET=target1
target1: all

target2: TARGET=target2
target2: all

EXEC=$($(TARGET)_EXEC)
SRC=$($(TARGET)_SRC)
OBJ=$(SRC:.c=.o)

all: $(EXEC)

$(EXEC): $(OBJ)
 $(CC) $(INCLUDES) -o $@ $^ $(LDFLAGS) $(LIBS)

%.o: %.c
 $(CC) -o $@ -c $< $(CFLAGS)

I would like to call the makefile with the target as an argument:

makefile target1

But then it seems that it does not find the subtarget:

make: Nothing to be done for 'target1'.

What am I doing wrong ?

linux variables makefile

share|improve this question

asked Mar 28 at 15:07

user3923073user3923073

5166 bronze badges

add a comment
 | 

I'm learning how to write makefiles and would like to create a makefile that can create multiple targets from multiple sources according to a given argument.

Here is what I tried so far:

# Compiler and others
CC=gcc

# Flags
CFLAGS = -g -c -Wall -DLOGFILE -D_REENTRANT

target1_EXEC = ../build/target1
target2_EXEC = ../build/target2

target1_SRC = ../source/target1
target2_SRC = ../source/target2

target1: TARGET=target1
target1: all

target2: TARGET=target2
target2: all

EXEC=$($(TARGET)_EXEC)
SRC=$($(TARGET)_SRC)
OBJ=$(SRC:.c=.o)

all: $(EXEC)

$(EXEC): $(OBJ)
 $(CC) $(INCLUDES) -o $@ $^ $(LDFLAGS) $(LIBS)

%.o: %.c
 $(CC) -o $@ -c $< $(CFLAGS)

I would like to call the makefile with the target as an argument:

makefile target1

But then it seems that it does not find the subtarget:

make: Nothing to be done for 'target1'.

What am I doing wrong ?

linux variables makefile

share|improve this question

asked Mar 28 at 15:07

user3923073user3923073

5166 bronze badges

# Compiler and others
CC=gcc

# Flags
CFLAGS = -g -c -Wall -DLOGFILE -D_REENTRANT

target1_EXEC = ../build/target1
target2_EXEC = ../build/target2

target1_SRC = ../source/target1
target2_SRC = ../source/target2

target1: TARGET=target1
target1: all

target2: TARGET=target2
target2: all

EXEC=$($(TARGET)_EXEC)
SRC=$($(TARGET)_SRC)
OBJ=$(SRC:.c=.o)

all: $(EXEC)

$(EXEC): $(OBJ)
 $(CC) $(INCLUDES) -o $@ $^ $(LDFLAGS) $(LIBS)

%.o: %.c
 $(CC) -o $@ -c $< $(CFLAGS)

makefile target1

make: Nothing to be done for 'target1'.

share|improve this question

asked Mar 28 at 15:07

user3923073user3923073

5166 bronze badges

share|improve this question

asked Mar 28 at 15:07

user3923073user3923073

5166 bronze badges

asked Mar 28 at 15:07

user3923073user3923073

5166 bronze badges

asked Mar 28 at 15:07

user3923073user3923073

5166 bronze badges