Styjun

I'm simply not sure how to modify the code. I know i need to add an inout port but I don't know how to do it. I have watched multiple tutorials but I can't figure it out.

module mem(
 input logic clk, we , // write enable bit, active low
 input logic [n-1:0] in ,
 input logic [m-1:0] addr ,
 output logic [n-1:0] out ) ;
 parameter n = 1, m = 1, k = 1 << m ; //data width, address width, size
 logic [n-1:0] memo [k-1:0] ; 
 // array of 2^m elements, each being an n-bit wide register
 assign out = memo[addr] ;
 always_ff @(posedge clk) begin
 if (! we ) memo[addr] = in ;
 end
endmodule

module stack(
 input logic clk , rst , // clock and reset
 input logic [1:0] op , //operation PUSH or POP (one-hot)
 input logic [n-1:0] pushval , // PUSH argument
 output logic [n-1:0] popval ) ; // POP result
 parameter n = 1, m = 1, k = 1<< m ; // data width, address width, size
 logic [m-1:0] addr ; // address for memory 
 logic up, down ; // breaking op down to 2 separate bits
 logic [n-1:0] in ; // input for memory
 logic [n-1:0] out ; // output from memory
 logic we ; // write enable signal for memory
 logic [m-1:0] addr1 ; // counter output
 assign up = (addr == m1'b1) ? 1'b0 : op[1] ;
 assign down = (addr == m1'b0) ? 1'b0 : op[0] ;
 assign in = (op == 2'b10) ? pushval : n1'b0;
 assign we = rst ? 1'b1 : !(up ^ down) ; 
 assign addr = (op == 2'b10) ? addr1 + 1'b1 : addr1 ;
 // instantiate memory module

 mem #(n,m,k) memory(clk, we, in, addr, out) ;

 assign popval = out ;
 // instantiate counter module

 udl #(m) counter(clk, rst, up, down, addr1) ;

endmodule

a bus can be designed with multiple writers and readers. An example is the following:

wire bus;
assign bus = wren1 ? data1 : 'z;
assign bus = wren2 ? data2 : 'z;

In the above example the bus is driven either by data or by a high impedance value. Real data always wins. Just make sure that enable signals are not turned on at the same time, or you will get 'x' as the bus value.

you can read the bus value in a normal way, for example:

always_latch
 if (rden1)
 val = bus;
...

you can pass the bus wire through an inout port, for example

 module mem(input clk, wren, [3:0] address, inout[3:0] data);
 logic [3:0]memory[15:0];
 assign data = !wren ? memory[address] : 'z;
 always_ff @(posedge clk) 
 if (wren)
 memory[address] <= data;
endmodule

similarly you can re-design you stack module.