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Verilog - Output of a module staying in unknown state when simulated
Verilog Signed Multiplication “loses” the Signed BitVerilog testbench design for my MSB downsampling moduleBooth's algorithm Verilog synthesizableVerilog simulation: all outputs xSimulation of Modelsim launching from Quartus doesn't work properlyWhy is there a difference in Output when using Event Control Statement and Wait statement for the following simple D Flipflop exampleVHDL Simulation Error on OutputsSignals not going forward from initial state in Verilog test benchCan't use else in verilog always blockWhy are my Verilog output registers only outputting “x”?
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When I try to simulate a module using Quartus prime's Simulation Waveform editor, the output of the module stays in the unknown state or don't care state ('X'). The module is the only one in the project along with the .vwf file.
Here is the module:
module pc (input clk, reset_n, branch, increment, input [7:0] newpc,
output reg [7:0] pc);
parameter RESET_LOCATION = 8'h00;
initial pc = 8'h00;
always @(posedge clk or posedge reset_n) begin
if (reset_n) begin
pc <= RESET_LOCATION;
end else begin
if (increment) begin
pc <= pc + 1;
end else if (branch) begin
pc <= newpc;
end
end
end
endmodule
And here is the simulation:
verilog fpga hdl quartus
asked Mar 25 at 18:22
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
add a comment |
When I try to simulate a module using Quartus prime's Simulation Waveform editor, the output of the module stays in the unknown state or don't care state ('X'). The module is the only one in the project along with the .vwf file.
Here is the module:
module pc (input clk, reset_n, branch, increment, input [7:0] newpc,
output reg [7:0] pc);
parameter RESET_LOCATION = 8'h00;
initial pc = 8'h00;
always @(posedge clk or posedge reset_n) begin
if (reset_n) begin
pc <= RESET_LOCATION;
end else begin
if (increment) begin
pc <= pc + 1;
end else if (branch) begin
pc <= newpc;
end
end
end
endmodule
And here is the simulation:
verilog fpga hdl quartus
asked Mar 25 at 18:22
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
Not that it would explain your simulation result, butreset_nis a strange name for an active-high reset signal.
– toolic
Mar 25 at 18:30
@toolic you're right it's supposed to be active low.
– alexanderd5398
Mar 25 at 18:36
add a comment |
When I try to simulate a module using Quartus prime's Simulation Waveform editor, the output of the module stays in the unknown state or don't care state ('X'). The module is the only one in the project along with the .vwf file.
Here is the module:
module pc (input clk, reset_n, branch, increment, input [7:0] newpc,
output reg [7:0] pc);
parameter RESET_LOCATION = 8'h00;
initial pc = 8'h00;
always @(posedge clk or posedge reset_n) begin
if (reset_n) begin
pc <= RESET_LOCATION;
end else begin
if (increment) begin
pc <= pc + 1;
end else if (branch) begin
pc <= newpc;
end
end
end
endmodule
And here is the simulation:
verilog fpga hdl quartus
asked Mar 25 at 18:22
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
When I try to simulate a module using Quartus prime's Simulation Waveform editor, the output of the module stays in the unknown state or don't care state ('X'). The module is the only one in the project along with the .vwf file.
Here is the module:
module pc (input clk, reset_n, branch, increment, input [7:0] newpc,
output reg [7:0] pc);
parameter RESET_LOCATION = 8'h00;
initial pc = 8'h00;
always @(posedge clk or posedge reset_n) begin
if (reset_n) begin
pc <= RESET_LOCATION;
end else begin
if (increment) begin
pc <= pc + 1;
end else if (branch) begin
pc <= newpc;
end
end
end
endmodule
And here is the simulation:
verilog fpga hdl quartus
verilog fpga hdl quartus
asked Mar 25 at 18:22
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
asked Mar 25 at 18:22
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
asked Mar 25 at 18:22
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
asked Mar 25 at 18:22
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
asked Mar 25 at 18:22
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
1291 silver badge12 bronze badges
Not that it would explain your simulation result, butreset_nis a strange name for an active-high reset signal.
– toolic
Mar 25 at 18:30
@toolic you're right it's supposed to be active low.
– alexanderd5398
Mar 25 at 18:36
add a comment |
Not that it would explain your simulation result, butreset_nis a strange name for an active-high reset signal.
– toolic
Mar 25 at 18:30
@toolic you're right it's supposed to be active low.
– alexanderd5398
Mar 25 at 18:36
Not that it would explain your simulation result, but
reset_n is a strange name for an active-high reset signal.– toolic
Mar 25 at 18:30
Not that it would explain your simulation result, but
reset_n is a strange name for an active-high reset signal.– toolic
Mar 25 at 18:30
@toolic you're right it's supposed to be active low.
– alexanderd5398
Mar 25 at 18:36
@toolic you're right it's supposed to be active low.
– alexanderd5398
Mar 25 at 18:36
add a comment |
1 Answer
1
active
oldest
votes
I found the solution...
I am not sure why, but I need to create a new .vwf whenever I change the top level entity.
answered Mar 25 at 18:30
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
add a comment |
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active
oldest
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oldest
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votes
I found the solution...
I am not sure why, but I need to create a new .vwf whenever I change the top level entity.
answered Mar 25 at 18:30
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
add a comment |
I found the solution...
I am not sure why, but I need to create a new .vwf whenever I change the top level entity.
answered Mar 25 at 18:30
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
add a comment |
I found the solution...
I am not sure why, but I need to create a new .vwf whenever I change the top level entity.
answered Mar 25 at 18:30
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
I found the solution...
I am not sure why, but I need to create a new .vwf whenever I change the top level entity.
answered Mar 25 at 18:30
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
answered Mar 25 at 18:30
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
answered Mar 25 at 18:30
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
answered Mar 25 at 18:30
alexanderd5398alexanderd5398
1291 silver badge12 bronze badges
1291 silver badge12 bronze badges
add a comment |
add a comment |
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Not that it would explain your simulation result, but
reset_nis a strange name for an active-high reset signal.– toolic
Mar 25 at 18:30
@toolic you're right it's supposed to be active low.
– alexanderd5398
Mar 25 at 18:36