Styjun

So i am supposed to implement a simple minimum cost function F with the usage of components. I have written what i believe to be the correct way according to my teacher's notes, but i get the error Error (12004): Port "out1" does not exist in primitive "AND2" of instance "U3", which i believe has something to do with the declaration of my components, but i cant find what's wrong. I just began VHDL two days ago so i am newbie to say the least ;p Any help would be very appreciated since i couldn"t find anything else on the internet. The reason i have more variables than i use is that i am going to add more code after i solve this error. :)

library ieee, my_func;
USE ieee.std_logic_1164.all, my_func.basic_func.all;
ENTITY Ergasia IS
 PORT (X1,X2,X3,X4,X5:IN std_logic;
 F,G:out std_logic);
END Ergasia;
architecture structural of Ergasia is

 component AND2 
 port(in1, in2: in std_logic;
 out1: out std_logic);
 end component;
 component AND3
 port(in1, in2, in3: in std_logic;
 out1: out std_logic);
 end component;
 component OR3
 port(in1, in2, in3: in std_logic;
 out1: out std_logic);
 end component;
 component NOT1
 port(in1: in std_logic;
 out1: out std_logic);
 end component;
 signal X1_NOT, X2_NOT, X3_NOT, X4_NOT, X5_NOT, B1, B2, B3:std_logic;
begin
 U0: NOT1 port map (X1,X1_NOT);
 U1: NOT1 port map (X2,X2_NOT);
 U2: NOT1 port map (X3,X3_NOT);
 U3: AND2 port map (X1_NOT,X2_NOT,B1);
 U4: AND2 port map (X2, X3_NOT, B2);
 U5: AND3 port map (X1, X2, X5, B3);
 U6: OR3 port map (B1, B2, B3,G);
end structural;

Also my basic_func is this:

library ieee;
use ieee.std_logic_1164.all;

package basic_func is

 component AND2
 port(in1,in2:in std_logic; out1:out std_logic);
 end component;

 component OR3
 port(in1,in2,in3:in std_logic; out1:out std_logic);
 end component;

 component AND3
 port(in1,in2,in3:in std_logic; out1:out std_logic);
 end component;
end package basic_func;



library ieee;
use ieee.std_logic_1164.all;
 entity AND2 is
 port(in1,in2:in std_logic; out1:out std_logic);
 end AND2;
 architecture model_and2 of AND2 is
 begin
 out1 <= in1 and in2;
 end model_and2;

library ieee;
use ieee.std_logic_1164.all;
 entity AND3 is
 port(in1,in2,in3:in std_logic;out1:out std_logic);
 end AND3;
 architecture model_and3 of AND3 is
 begin
 out1 <= (in1 and in2) and in3;
 end model_and3;

library ieee;
use ieee.std_logic_1164.all; 
 entity OR3 is
 port(in1,in2,in3:in std_logic;out1:out std_logic);
 end OR3;
 architecture model_or3 of OR3 is
 begin
 out1 <= (in1 and in2) and in3;
 end model_or3;