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What is the meaning of $(Q)@: in Makefile


What does @: (at symbol colon) mean in a Makefile?What is the difference between the GNU Makefile variable assignments =, ?=, := and +=?How do I write the 'cd' command in a makefile?What is the purpose of .PHONY in a makefile?What do the makefile symbols $@ and $< mean?Sources from subdirectories in MakefileWhat does @: (at symbol colon) mean in a Makefile?What are the major differences between makefile and CMakeListHow to print out a variable in makefileAssignment of variable in GNU MakefileIncluding sub makefiles in a master makefile: variables changed in sub makefile do not reflect in master makefile






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4















I've read in linux Makefile:



$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
$(Q)@:


What is the meaning of "$(Q)@:"?



I'm trying to google it, but google always crappy if the search using some weird character. So in the end i can't found any Manual about it.










share|improve this question




























    4















    I've read in linux Makefile:



    $(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
    $(Q)@:


    What is the meaning of "$(Q)@:"?



    I'm trying to google it, but google always crappy if the search using some weird character. So in the end i can't found any Manual about it.










    share|improve this question
























      4












      4








      4


      0






      I've read in linux Makefile:



      $(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
      $(Q)@:


      What is the meaning of "$(Q)@:"?



      I'm trying to google it, but google always crappy if the search using some weird character. So in the end i can't found any Manual about it.










      share|improve this question














      I've read in linux Makefile:



      $(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
      $(Q)@:


      What is the meaning of "$(Q)@:"?



      I'm trying to google it, but google always crappy if the search using some weird character. So in the end i can't found any Manual about it.







      makefile gnu-make






      share|improve this question













      share|improve this question











      share|improve this question




      share|improve this question










      asked Apr 9 '16 at 18:55









      nafsakanafsaka

      509717




      509717






















          2 Answers
          2






          active

          oldest

          votes


















          3














          After looking in the code. Q is defined somewhere after those line. Since makefile have peculiar concept of variable (which is expandable), it can be implement in anywhere. Q is used to whether show message or not (Q maybe for Quiet).



          ifeq ($(KBUILD_VERBOSE),1)
          quiet =
          Q =
          else
          quiet=quiet_
          Q = @
          endif


          And for the last @: this means do-nothing-output-nothing.



          So the conclusion $(Q)@: simply do-nothing-output-nothing.






          share|improve this answer
































            0














            To reinforce and expand on what nafsaka found:
            Sometimes Makefiles are written like this:




            target:
            rm -rf $(DIRECTORY)
            $(Q)$(MAKE) all



            And Q will be defined as @ or nothing for example:




            V ?= 0
            ifeq ($(V), 0)
            Q = @
            else
            Q =
            endif



            If a target action is preceded by @ then make won't display it when run. Here's the GNU make documentation on that subject: Recipe Echoing



            In this case you need to define V=1 before running make to see commands as they're run (This is very common).



            Another wrinkle: Look for "include file.mk" statements in your Makefile, which is where V and Q were defined in my case. Here's the GNU make documentation on include: Including Other Makefiles






            share|improve this answer























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              2 Answers
              2






              active

              oldest

              votes









              active

              oldest

              votes






              active

              oldest

              votes









              3














              After looking in the code. Q is defined somewhere after those line. Since makefile have peculiar concept of variable (which is expandable), it can be implement in anywhere. Q is used to whether show message or not (Q maybe for Quiet).



              ifeq ($(KBUILD_VERBOSE),1)
              quiet =
              Q =
              else
              quiet=quiet_
              Q = @
              endif


              And for the last @: this means do-nothing-output-nothing.



              So the conclusion $(Q)@: simply do-nothing-output-nothing.






              share|improve this answer





























                3














                After looking in the code. Q is defined somewhere after those line. Since makefile have peculiar concept of variable (which is expandable), it can be implement in anywhere. Q is used to whether show message or not (Q maybe for Quiet).



                ifeq ($(KBUILD_VERBOSE),1)
                quiet =
                Q =
                else
                quiet=quiet_
                Q = @
                endif


                And for the last @: this means do-nothing-output-nothing.



                So the conclusion $(Q)@: simply do-nothing-output-nothing.






                share|improve this answer



























                  3












                  3








                  3







                  After looking in the code. Q is defined somewhere after those line. Since makefile have peculiar concept of variable (which is expandable), it can be implement in anywhere. Q is used to whether show message or not (Q maybe for Quiet).



                  ifeq ($(KBUILD_VERBOSE),1)
                  quiet =
                  Q =
                  else
                  quiet=quiet_
                  Q = @
                  endif


                  And for the last @: this means do-nothing-output-nothing.



                  So the conclusion $(Q)@: simply do-nothing-output-nothing.






                  share|improve this answer















                  After looking in the code. Q is defined somewhere after those line. Since makefile have peculiar concept of variable (which is expandable), it can be implement in anywhere. Q is used to whether show message or not (Q maybe for Quiet).



                  ifeq ($(KBUILD_VERBOSE),1)
                  quiet =
                  Q =
                  else
                  quiet=quiet_
                  Q = @
                  endif


                  And for the last @: this means do-nothing-output-nothing.



                  So the conclusion $(Q)@: simply do-nothing-output-nothing.







                  share|improve this answer














                  share|improve this answer



                  share|improve this answer








                  edited May 23 '17 at 10:29









                  Community

                  11




                  11










                  answered Apr 9 '16 at 20:03









                  nafsakanafsaka

                  509717




                  509717























                      0














                      To reinforce and expand on what nafsaka found:
                      Sometimes Makefiles are written like this:




                      target:
                      rm -rf $(DIRECTORY)
                      $(Q)$(MAKE) all



                      And Q will be defined as @ or nothing for example:




                      V ?= 0
                      ifeq ($(V), 0)
                      Q = @
                      else
                      Q =
                      endif



                      If a target action is preceded by @ then make won't display it when run. Here's the GNU make documentation on that subject: Recipe Echoing



                      In this case you need to define V=1 before running make to see commands as they're run (This is very common).



                      Another wrinkle: Look for "include file.mk" statements in your Makefile, which is where V and Q were defined in my case. Here's the GNU make documentation on include: Including Other Makefiles






                      share|improve this answer



























                        0














                        To reinforce and expand on what nafsaka found:
                        Sometimes Makefiles are written like this:




                        target:
                        rm -rf $(DIRECTORY)
                        $(Q)$(MAKE) all



                        And Q will be defined as @ or nothing for example:




                        V ?= 0
                        ifeq ($(V), 0)
                        Q = @
                        else
                        Q =
                        endif



                        If a target action is preceded by @ then make won't display it when run. Here's the GNU make documentation on that subject: Recipe Echoing



                        In this case you need to define V=1 before running make to see commands as they're run (This is very common).



                        Another wrinkle: Look for "include file.mk" statements in your Makefile, which is where V and Q were defined in my case. Here's the GNU make documentation on include: Including Other Makefiles






                        share|improve this answer

























                          0












                          0








                          0







                          To reinforce and expand on what nafsaka found:
                          Sometimes Makefiles are written like this:




                          target:
                          rm -rf $(DIRECTORY)
                          $(Q)$(MAKE) all



                          And Q will be defined as @ or nothing for example:




                          V ?= 0
                          ifeq ($(V), 0)
                          Q = @
                          else
                          Q =
                          endif



                          If a target action is preceded by @ then make won't display it when run. Here's the GNU make documentation on that subject: Recipe Echoing



                          In this case you need to define V=1 before running make to see commands as they're run (This is very common).



                          Another wrinkle: Look for "include file.mk" statements in your Makefile, which is where V and Q were defined in my case. Here's the GNU make documentation on include: Including Other Makefiles






                          share|improve this answer













                          To reinforce and expand on what nafsaka found:
                          Sometimes Makefiles are written like this:




                          target:
                          rm -rf $(DIRECTORY)
                          $(Q)$(MAKE) all



                          And Q will be defined as @ or nothing for example:




                          V ?= 0
                          ifeq ($(V), 0)
                          Q = @
                          else
                          Q =
                          endif



                          If a target action is preceded by @ then make won't display it when run. Here's the GNU make documentation on that subject: Recipe Echoing



                          In this case you need to define V=1 before running make to see commands as they're run (This is very common).



                          Another wrinkle: Look for "include file.mk" statements in your Makefile, which is where V and Q were defined in my case. Here's the GNU make documentation on include: Including Other Makefiles







                          share|improve this answer












                          share|improve this answer



                          share|improve this answer










                          answered Mar 22 at 23:20









                          Brad DreBrad Dre

                          1,3721016




                          1,3721016



























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