Alternative for sw MIPS instructionIs mars MIPS simulator Big or Little EndianWhat's the purpose of the LEA instruction?Spim Instruction divisionHow do I achieve the theoretical maximum of 4 FLOPs per cycle?Replacing a 32-bit loop counter with 64-bit introduces crazy performance deviationsMIPS Translation of li pseudo commandmips store instruction offset, and move instructionLoad Doubleword Pseudoinstruction in MIPSMIPS instruction and machine codeMips assembly save return value into specific adressWhat is the mips-command to load 4 bytes at the same time into a register?
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Alternative for sw MIPS instruction
Is mars MIPS simulator Big or Little EndianWhat's the purpose of the LEA instruction?Spim Instruction divisionHow do I achieve the theoretical maximum of 4 FLOPs per cycle?Replacing a 32-bit loop counter with 64-bit introduces crazy performance deviationsMIPS Translation of li pseudo commandmips store instruction offset, and move instructionLoad Doubleword Pseudoinstruction in MIPSMIPS instruction and machine codeMips assembly save return value into specific adressWhat is the mips-command to load 4 bytes at the same time into a register?
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What is an alternative to save a word from register into RAM?
For example i can explain lw command as lui, ori. How could be 4 Bytes stored into RAM without using sw?
assembly mips instructions
asked Mar 28 at 19:16
dancingsushiidancingsushii
31 bronze badge
add a comment
|
What is an alternative to save a word from register into RAM?
For example i can explain lw command as lui, ori. How could be 4 Bytes stored into RAM without using sw?
assembly mips instructions
asked Mar 28 at 19:16
dancingsushiidancingsushii
31 bronze badge
2
No you can't.lwis not the same asluiandori. You are probably thinking ofla.
– Jester
Mar 28 at 19:17
Why not? lw loads one word to register. Is not same, but it's possible to do the same with lui and ori. And i'm looking for same instructions set, that could exchange sw.
– dancingsushii
Mar 28 at 19:34
3
No you can not do the same withluiandori.lwaccesses memory, the alternatives don't. You can only uselui/orito load a known compile-time constant.lwreads memory. Tell me, how do you write for examplelw $a0, ($t0)usinglui/ori?
– Jester
Mar 28 at 19:36
4
"How could be 4 Bytes stored into RAM without using sw?" By using 4sbinstructions, or 2shinstructions.
– Michael
Mar 28 at 20:45
add a comment
|
What is an alternative to save a word from register into RAM?
For example i can explain lw command as lui, ori. How could be 4 Bytes stored into RAM without using sw?
assembly mips instructions
asked Mar 28 at 19:16
dancingsushiidancingsushii
31 bronze badge
What is an alternative to save a word from register into RAM?
For example i can explain lw command as lui, ori. How could be 4 Bytes stored into RAM without using sw?
assembly mips instructions
assembly mips instructions
asked Mar 28 at 19:16
dancingsushiidancingsushii
31 bronze badge
asked Mar 28 at 19:16
dancingsushiidancingsushii
31 bronze badge
asked Mar 28 at 19:16
dancingsushiidancingsushii
31 bronze badge
asked Mar 28 at 19:16
dancingsushiidancingsushii
31 bronze badge
asked Mar 28 at 19:16
dancingsushiidancingsushii
31 bronze badge
31 bronze badge
2
No you can't.lwis not the same asluiandori. You are probably thinking ofla.
– Jester
Mar 28 at 19:17
Why not? lw loads one word to register. Is not same, but it's possible to do the same with lui and ori. And i'm looking for same instructions set, that could exchange sw.
– dancingsushii
Mar 28 at 19:34
3
No you can not do the same withluiandori.lwaccesses memory, the alternatives don't. You can only uselui/orito load a known compile-time constant.lwreads memory. Tell me, how do you write for examplelw $a0, ($t0)usinglui/ori?
– Jester
Mar 28 at 19:36
4
"How could be 4 Bytes stored into RAM without using sw?" By using 4sbinstructions, or 2shinstructions.
– Michael
Mar 28 at 20:45
add a comment
|
2
No you can't.lwis not the same asluiandori. You are probably thinking ofla.
– Jester
Mar 28 at 19:17
Why not? lw loads one word to register. Is not same, but it's possible to do the same with lui and ori. And i'm looking for same instructions set, that could exchange sw.
– dancingsushii
Mar 28 at 19:34
3
No you can not do the same withluiandori.lwaccesses memory, the alternatives don't. You can only uselui/orito load a known compile-time constant.lwreads memory. Tell me, how do you write for examplelw $a0, ($t0)usinglui/ori?
– Jester
Mar 28 at 19:36
4
"How could be 4 Bytes stored into RAM without using sw?" By using 4sbinstructions, or 2shinstructions.
– Michael
Mar 28 at 20:45
2
2
No you can't.
lw is not the same as lui and ori. You are probably thinking of la.– Jester
Mar 28 at 19:17
No you can't.
lw is not the same as lui and ori. You are probably thinking of la.– Jester
Mar 28 at 19:17
Why not? lw loads one word to register. Is not same, but it's possible to do the same with lui and ori. And i'm looking for same instructions set, that could exchange sw.
– dancingsushii
Mar 28 at 19:34
Why not? lw loads one word to register. Is not same, but it's possible to do the same with lui and ori. And i'm looking for same instructions set, that could exchange sw.
– dancingsushii
Mar 28 at 19:34
3
3
No you can not do the same with
lui and ori. lw accesses memory, the alternatives don't. You can only use lui/ori to load a known compile-time constant. lw reads memory. Tell me, how do you write for example lw $a0, ($t0) using lui/ori?– Jester
Mar 28 at 19:36
No you can not do the same with
lui and ori. lw accesses memory, the alternatives don't. You can only use lui/ori to load a known compile-time constant. lw reads memory. Tell me, how do you write for example lw $a0, ($t0) using lui/ori?– Jester
Mar 28 at 19:36
4
4
"How could be 4 Bytes stored into RAM without using sw?" By using 4
sb instructions, or 2 sh instructions.– Michael
Mar 28 at 20:45
"How could be 4 Bytes stored into RAM without using sw?" By using 4
sb instructions, or 2 sh instructions.– Michael
Mar 28 at 20:45
add a comment
|
1 Answer
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First of all, lui/ori construct a value in a register from an immediate, without accessing data memory. They're not in any way equivalent to lw. Perhaps you're thinking of li, which is a pseudo-instruction for lui and/or ori. Only load instructions can access memory; immediate ALU instructions take data from the instruction itself but that doesn't really count.
MIPS provides pairs of instructions for loading/storing the left and right parts of an unaligned word. The stores are SWL (left) and SWR (store word right).
Their effect depends on the endian mode of your MIPS (it support big and little endian). MARS simulates a MIPS in little-endian mode.
In little-endian mode, SWL $t1, buf stores the high byte of $t1 to the first byte of buf, for an aligned buf.
In little-endian mode, on an address that is aligned (like sw requires1), SWR acts like SW, storing all 4 bytes.
These instructions are interesting because they can modify 1 to 4 bytes in a word. Including 3 bytes, which you can't do with one sb (byte) or sh (half-word).
http://db.cs.duke.edu/courses/fall02/cps104/homework/lwswlr.html explains how to use the SPARC instructions of the same name. I think MIPS (in big-endian mode) would be the same, and MIPS in little-endian mode like MARS simulates is like that but reversed.
So in big-endian mode, I think swl is equivalent to sw for aligned addresses, but I haven't tested.
Footnote 1:
MIPS32R6 removed LWL/R, and requires LW to support unaligned store / load. Wikipedia doesn't mention stores for that, only loads.
See also https://www.linux-mips.org/wiki/Alignment: Linux MIPS has a kernel option to emulate unaligned load/store instead of delivering SIGBUS on unaligned LW or SW.
answered Mar 29 at 4:28
Peter CordesPeter Cordes
158k23 gold badges254 silver badges406 bronze badges
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First of all, lui/ori construct a value in a register from an immediate, without accessing data memory. They're not in any way equivalent to lw. Perhaps you're thinking of li, which is a pseudo-instruction for lui and/or ori. Only load instructions can access memory; immediate ALU instructions take data from the instruction itself but that doesn't really count.
MIPS provides pairs of instructions for loading/storing the left and right parts of an unaligned word. The stores are SWL (left) and SWR (store word right).
Their effect depends on the endian mode of your MIPS (it support big and little endian). MARS simulates a MIPS in little-endian mode.
In little-endian mode, SWL $t1, buf stores the high byte of $t1 to the first byte of buf, for an aligned buf.
In little-endian mode, on an address that is aligned (like sw requires1), SWR acts like SW, storing all 4 bytes.
These instructions are interesting because they can modify 1 to 4 bytes in a word. Including 3 bytes, which you can't do with one sb (byte) or sh (half-word).
http://db.cs.duke.edu/courses/fall02/cps104/homework/lwswlr.html explains how to use the SPARC instructions of the same name. I think MIPS (in big-endian mode) would be the same, and MIPS in little-endian mode like MARS simulates is like that but reversed.
So in big-endian mode, I think swl is equivalent to sw for aligned addresses, but I haven't tested.
Footnote 1:
MIPS32R6 removed LWL/R, and requires LW to support unaligned store / load. Wikipedia doesn't mention stores for that, only loads.
See also https://www.linux-mips.org/wiki/Alignment: Linux MIPS has a kernel option to emulate unaligned load/store instead of delivering SIGBUS on unaligned LW or SW.
answered Mar 29 at 4:28
Peter CordesPeter Cordes
158k23 gold badges254 silver badges406 bronze badges
add a comment
|
First of all, lui/ori construct a value in a register from an immediate, without accessing data memory. They're not in any way equivalent to lw. Perhaps you're thinking of li, which is a pseudo-instruction for lui and/or ori. Only load instructions can access memory; immediate ALU instructions take data from the instruction itself but that doesn't really count.
MIPS provides pairs of instructions for loading/storing the left and right parts of an unaligned word. The stores are SWL (left) and SWR (store word right).
Their effect depends on the endian mode of your MIPS (it support big and little endian). MARS simulates a MIPS in little-endian mode.
In little-endian mode, SWL $t1, buf stores the high byte of $t1 to the first byte of buf, for an aligned buf.
In little-endian mode, on an address that is aligned (like sw requires1), SWR acts like SW, storing all 4 bytes.
These instructions are interesting because they can modify 1 to 4 bytes in a word. Including 3 bytes, which you can't do with one sb (byte) or sh (half-word).
http://db.cs.duke.edu/courses/fall02/cps104/homework/lwswlr.html explains how to use the SPARC instructions of the same name. I think MIPS (in big-endian mode) would be the same, and MIPS in little-endian mode like MARS simulates is like that but reversed.
So in big-endian mode, I think swl is equivalent to sw for aligned addresses, but I haven't tested.
Footnote 1:
MIPS32R6 removed LWL/R, and requires LW to support unaligned store / load. Wikipedia doesn't mention stores for that, only loads.
See also https://www.linux-mips.org/wiki/Alignment: Linux MIPS has a kernel option to emulate unaligned load/store instead of delivering SIGBUS on unaligned LW or SW.
answered Mar 29 at 4:28
Peter CordesPeter Cordes
158k23 gold badges254 silver badges406 bronze badges
add a comment
|
First of all, lui/ori construct a value in a register from an immediate, without accessing data memory. They're not in any way equivalent to lw. Perhaps you're thinking of li, which is a pseudo-instruction for lui and/or ori. Only load instructions can access memory; immediate ALU instructions take data from the instruction itself but that doesn't really count.
MIPS provides pairs of instructions for loading/storing the left and right parts of an unaligned word. The stores are SWL (left) and SWR (store word right).
Their effect depends on the endian mode of your MIPS (it support big and little endian). MARS simulates a MIPS in little-endian mode.
In little-endian mode, SWL $t1, buf stores the high byte of $t1 to the first byte of buf, for an aligned buf.
In little-endian mode, on an address that is aligned (like sw requires1), SWR acts like SW, storing all 4 bytes.
These instructions are interesting because they can modify 1 to 4 bytes in a word. Including 3 bytes, which you can't do with one sb (byte) or sh (half-word).
http://db.cs.duke.edu/courses/fall02/cps104/homework/lwswlr.html explains how to use the SPARC instructions of the same name. I think MIPS (in big-endian mode) would be the same, and MIPS in little-endian mode like MARS simulates is like that but reversed.
So in big-endian mode, I think swl is equivalent to sw for aligned addresses, but I haven't tested.
Footnote 1:
MIPS32R6 removed LWL/R, and requires LW to support unaligned store / load. Wikipedia doesn't mention stores for that, only loads.
See also https://www.linux-mips.org/wiki/Alignment: Linux MIPS has a kernel option to emulate unaligned load/store instead of delivering SIGBUS on unaligned LW or SW.
answered Mar 29 at 4:28
Peter CordesPeter Cordes
158k23 gold badges254 silver badges406 bronze badges
First of all, lui/ori construct a value in a register from an immediate, without accessing data memory. They're not in any way equivalent to lw. Perhaps you're thinking of li, which is a pseudo-instruction for lui and/or ori. Only load instructions can access memory; immediate ALU instructions take data from the instruction itself but that doesn't really count.
MIPS provides pairs of instructions for loading/storing the left and right parts of an unaligned word. The stores are SWL (left) and SWR (store word right).
Their effect depends on the endian mode of your MIPS (it support big and little endian). MARS simulates a MIPS in little-endian mode.
In little-endian mode, SWL $t1, buf stores the high byte of $t1 to the first byte of buf, for an aligned buf.
In little-endian mode, on an address that is aligned (like sw requires1), SWR acts like SW, storing all 4 bytes.
These instructions are interesting because they can modify 1 to 4 bytes in a word. Including 3 bytes, which you can't do with one sb (byte) or sh (half-word).
http://db.cs.duke.edu/courses/fall02/cps104/homework/lwswlr.html explains how to use the SPARC instructions of the same name. I think MIPS (in big-endian mode) would be the same, and MIPS in little-endian mode like MARS simulates is like that but reversed.
So in big-endian mode, I think swl is equivalent to sw for aligned addresses, but I haven't tested.
Footnote 1:
MIPS32R6 removed LWL/R, and requires LW to support unaligned store / load. Wikipedia doesn't mention stores for that, only loads.
See also https://www.linux-mips.org/wiki/Alignment: Linux MIPS has a kernel option to emulate unaligned load/store instead of delivering SIGBUS on unaligned LW or SW.
answered Mar 29 at 4:28
Peter CordesPeter Cordes
158k23 gold badges254 silver badges406 bronze badges
answered Mar 29 at 4:28
Peter CordesPeter Cordes
158k23 gold badges254 silver badges406 bronze badges
answered Mar 29 at 4:28
Peter CordesPeter Cordes
158k23 gold badges254 silver badges406 bronze badges
answered Mar 29 at 4:28
Peter CordesPeter Cordes
158k23 gold badges254 silver badges406 bronze badges
158k23 gold badges254 silver badges406 bronze badges
add a comment
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2
No you can't.
lwis not the same asluiandori. You are probably thinking ofla.– Jester
Mar 28 at 19:17
Why not? lw loads one word to register. Is not same, but it's possible to do the same with lui and ori. And i'm looking for same instructions set, that could exchange sw.
– dancingsushii
Mar 28 at 19:34
3
No you can not do the same with
luiandori.lwaccesses memory, the alternatives don't. You can only uselui/orito load a known compile-time constant.lwreads memory. Tell me, how do you write for examplelw $a0, ($t0)usinglui/ori?– Jester
Mar 28 at 19:36
4
"How could be 4 Bytes stored into RAM without using sw?" By using 4
sbinstructions, or 2shinstructions.– Michael
Mar 28 at 20:45