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How is the bootstrap processor (BSP) selected on Intel ring and mesh architectures
How do you use gcc to generate assembly code in Intel syntax?Where is the L1 memory cache of Intel x86 processors documented?Why does Intel hide internal RISC core in their processors?How can I write self-modifying code that runs efficiently on modern x64 processors?When can the CPU ignore the LOCK prefix and use cache coherency?Are Intel x86_64 processors not only pipelined architecture, but also superscalar?Why is the loop instruction slow? Couldn't Intel have implemented it efficiently?EIP register intel architectureHow exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistentAre write-combining buffers used for normal writes to WB memory regions on Intel?
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Section 2.13.2 mentions that the arbitration ID is used to determine which processor issues the no-op cycle first and I have seen this on multiple sources and the intel manual. The intel manual that references the MP initialisation sequence only addresses Pentium 4 when when there was a 'system bus' and before that there was originally an 'APIC bus'. I am under the impression that arbitration ID was only needed in those architectures where multiple cpus shared the same bus. But now, with the ring bus architecture, arbitration is done by sensing an empty slot on the ring bus and placing the transaction on it and it moves round at one stop per cycle meaning arbitration is no longer required.
What's interesting is Section 2.13.2 is part of a document that speaks about Intel ME and the PCH, so it is obviously speaking about Nehalem and recent but to say that the APIC ArbID is used, perhaps it is indeed only talking about Nehalem or Westmere.
So I ask, how is the BSP selected on ring and indeed mesh architectures? My thought was that it could use cache as RAM and if cache coherency does function in no fill mode then they could race for a mutex
x86 intel cpu-architecture boot multicore
edited Mar 23 at 21:36
Peter Cordes
140k20214355
asked Mar 23 at 17:54
Lewis KelseyLewis Kelsey
458414
add a comment |
Section 2.13.2 mentions that the arbitration ID is used to determine which processor issues the no-op cycle first and I have seen this on multiple sources and the intel manual. The intel manual that references the MP initialisation sequence only addresses Pentium 4 when when there was a 'system bus' and before that there was originally an 'APIC bus'. I am under the impression that arbitration ID was only needed in those architectures where multiple cpus shared the same bus. But now, with the ring bus architecture, arbitration is done by sensing an empty slot on the ring bus and placing the transaction on it and it moves round at one stop per cycle meaning arbitration is no longer required.
What's interesting is Section 2.13.2 is part of a document that speaks about Intel ME and the PCH, so it is obviously speaking about Nehalem and recent but to say that the APIC ArbID is used, perhaps it is indeed only talking about Nehalem or Westmere.
So I ask, how is the BSP selected on ring and indeed mesh architectures? My thought was that it could use cache as RAM and if cache coherency does function in no fill mode then they could race for a mutex
x86 intel cpu-architecture boot multicore
edited Mar 23 at 21:36
Peter Cordes
140k20214355
asked Mar 23 at 17:54
Lewis KelseyLewis Kelsey
458414
add a comment |
Section 2.13.2 mentions that the arbitration ID is used to determine which processor issues the no-op cycle first and I have seen this on multiple sources and the intel manual. The intel manual that references the MP initialisation sequence only addresses Pentium 4 when when there was a 'system bus' and before that there was originally an 'APIC bus'. I am under the impression that arbitration ID was only needed in those architectures where multiple cpus shared the same bus. But now, with the ring bus architecture, arbitration is done by sensing an empty slot on the ring bus and placing the transaction on it and it moves round at one stop per cycle meaning arbitration is no longer required.
What's interesting is Section 2.13.2 is part of a document that speaks about Intel ME and the PCH, so it is obviously speaking about Nehalem and recent but to say that the APIC ArbID is used, perhaps it is indeed only talking about Nehalem or Westmere.
So I ask, how is the BSP selected on ring and indeed mesh architectures? My thought was that it could use cache as RAM and if cache coherency does function in no fill mode then they could race for a mutex
x86 intel cpu-architecture boot multicore
edited Mar 23 at 21:36
Peter Cordes
140k20214355
asked Mar 23 at 17:54
Lewis KelseyLewis Kelsey
458414
Section 2.13.2 mentions that the arbitration ID is used to determine which processor issues the no-op cycle first and I have seen this on multiple sources and the intel manual. The intel manual that references the MP initialisation sequence only addresses Pentium 4 when when there was a 'system bus' and before that there was originally an 'APIC bus'. I am under the impression that arbitration ID was only needed in those architectures where multiple cpus shared the same bus. But now, with the ring bus architecture, arbitration is done by sensing an empty slot on the ring bus and placing the transaction on it and it moves round at one stop per cycle meaning arbitration is no longer required.
What's interesting is Section 2.13.2 is part of a document that speaks about Intel ME and the PCH, so it is obviously speaking about Nehalem and recent but to say that the APIC ArbID is used, perhaps it is indeed only talking about Nehalem or Westmere.
So I ask, how is the BSP selected on ring and indeed mesh architectures? My thought was that it could use cache as RAM and if cache coherency does function in no fill mode then they could race for a mutex
x86 intel cpu-architecture boot multicore
x86 intel cpu-architecture boot multicore
edited Mar 23 at 21:36
Peter Cordes
140k20214355
asked Mar 23 at 17:54
Lewis KelseyLewis Kelsey
458414
edited Mar 23 at 21:36
Peter Cordes
140k20214355
asked Mar 23 at 17:54
Lewis KelseyLewis Kelsey
458414
edited Mar 23 at 21:36
Peter Cordes
140k20214355
edited Mar 23 at 21:36
Peter Cordes
140k20214355
edited Mar 23 at 21:36
Peter Cordes
140k20214355
140k20214355
asked Mar 23 at 17:54
Lewis KelseyLewis Kelsey
458414
asked Mar 23 at 17:54
Lewis KelseyLewis Kelsey
458414
asked Mar 23 at 17:54
Lewis KelseyLewis Kelsey
458414
458414
add a comment |
add a comment |
1 Answer
1
active
oldest
votes
I assume it's just hard-wired that one of the cores is the BSP. I don't think they other cores even power up until you send them an IPI, and they certainly wouldn't be running code that tries to take a mutex in cache to sort this out. The other cores probably come up in a HALT-like state that waits for an interrupt.
(But probably a deep sleep C-state like C7 or something, unlike the actual HALT instruction, so if the OS never wakes up some of the cores, putting the woken cores to sleep can let the whole package go into a deep sleep state.)
For multi-socket systems, presumably one socket is special somehow.
answered Mar 23 at 21:42
Peter CordesPeter Cordes
140k20214355
1
I don't think hard-wiring the BSP works. My understanding is that we don't even know which of the physical cores will be working properly until after fabricating the chip (and marketing it as such). Otherwise, the hard-wired core might be the faulty one. So there is a need for a boot-time mechanism to choose one of the (properly working) logical cores as the BSP. I also don't understand the question. There can be many transactions on the ring or mesh at any point in time. I'm not sure why @LewisKelsey thinks that the arbitration ID is not needed.
– Hadi Brais
Mar 29 at 9:02
1
Good point. I looked at the manual of Supermicro X8DTN, which is a dual socket motherboard. The tables for optimal memory population shown on page 30 and 31 indicate that any of the two sockets can be populated or both. So yeah I think there needs to be some negotiation between the sockets (if there is more than one).
– Hadi Brais
Mar 29 at 9:31
1
@LewisKelsey Let's very carefully read how Section 8.4.3 of Volume 3 describes the BSP selection process. First, each processor is assigned a unique APIC ID (each logical core has a local APIC). Second, each logical processor is assigned an arbitration priority based on the APIC ID (which could be equal to the APIC ID). Third, each processor executes the built-in self test. Fourth, on modern Intel processors, each logical processor issues a NOP Special Cycle on the system bus. What does this mean?...
– Hadi Brais
Mar 29 at 19:13
1
...The Special Cycle is a type of transaction that is handled by the Ubox unit in the system agent as I'll describe shortly. In modern Intel processors, the system bus is basically the QPI interconnect. So putting it together, this means that each logical core issues a Special Cycle request to the Ubox and each such request is tagged with the arbitration priority of the logical core. The Ubox receives all of these requests (from the internal cores of the respective socket). Each Ubox chooses the request with the highest priority and then itself arbitrates for the QPI bus master lock...
– Hadi Brais
Mar 29 at 19:13
1
@LewisKelsey The Ubox is discussed in the Intel uncore manuals. The LIKWID documentation on the Ubox is actually from the manuals.
– Hadi Brais
Mar 31 at 17:25
|
show 12 more comments
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I assume it's just hard-wired that one of the cores is the BSP. I don't think they other cores even power up until you send them an IPI, and they certainly wouldn't be running code that tries to take a mutex in cache to sort this out. The other cores probably come up in a HALT-like state that waits for an interrupt.
(But probably a deep sleep C-state like C7 or something, unlike the actual HALT instruction, so if the OS never wakes up some of the cores, putting the woken cores to sleep can let the whole package go into a deep sleep state.)
For multi-socket systems, presumably one socket is special somehow.
answered Mar 23 at 21:42
Peter CordesPeter Cordes
140k20214355
1
I don't think hard-wiring the BSP works. My understanding is that we don't even know which of the physical cores will be working properly until after fabricating the chip (and marketing it as such). Otherwise, the hard-wired core might be the faulty one. So there is a need for a boot-time mechanism to choose one of the (properly working) logical cores as the BSP. I also don't understand the question. There can be many transactions on the ring or mesh at any point in time. I'm not sure why @LewisKelsey thinks that the arbitration ID is not needed.
– Hadi Brais
Mar 29 at 9:02
1
Good point. I looked at the manual of Supermicro X8DTN, which is a dual socket motherboard. The tables for optimal memory population shown on page 30 and 31 indicate that any of the two sockets can be populated or both. So yeah I think there needs to be some negotiation between the sockets (if there is more than one).
– Hadi Brais
Mar 29 at 9:31
1
@LewisKelsey Let's very carefully read how Section 8.4.3 of Volume 3 describes the BSP selection process. First, each processor is assigned a unique APIC ID (each logical core has a local APIC). Second, each logical processor is assigned an arbitration priority based on the APIC ID (which could be equal to the APIC ID). Third, each processor executes the built-in self test. Fourth, on modern Intel processors, each logical processor issues a NOP Special Cycle on the system bus. What does this mean?...
– Hadi Brais
Mar 29 at 19:13
1
...The Special Cycle is a type of transaction that is handled by the Ubox unit in the system agent as I'll describe shortly. In modern Intel processors, the system bus is basically the QPI interconnect. So putting it together, this means that each logical core issues a Special Cycle request to the Ubox and each such request is tagged with the arbitration priority of the logical core. The Ubox receives all of these requests (from the internal cores of the respective socket). Each Ubox chooses the request with the highest priority and then itself arbitrates for the QPI bus master lock...
– Hadi Brais
Mar 29 at 19:13
1
@LewisKelsey The Ubox is discussed in the Intel uncore manuals. The LIKWID documentation on the Ubox is actually from the manuals.
– Hadi Brais
Mar 31 at 17:25
|
show 12 more comments
I assume it's just hard-wired that one of the cores is the BSP. I don't think they other cores even power up until you send them an IPI, and they certainly wouldn't be running code that tries to take a mutex in cache to sort this out. The other cores probably come up in a HALT-like state that waits for an interrupt.
(But probably a deep sleep C-state like C7 or something, unlike the actual HALT instruction, so if the OS never wakes up some of the cores, putting the woken cores to sleep can let the whole package go into a deep sleep state.)
For multi-socket systems, presumably one socket is special somehow.
answered Mar 23 at 21:42
Peter CordesPeter Cordes
140k20214355
1
I don't think hard-wiring the BSP works. My understanding is that we don't even know which of the physical cores will be working properly until after fabricating the chip (and marketing it as such). Otherwise, the hard-wired core might be the faulty one. So there is a need for a boot-time mechanism to choose one of the (properly working) logical cores as the BSP. I also don't understand the question. There can be many transactions on the ring or mesh at any point in time. I'm not sure why @LewisKelsey thinks that the arbitration ID is not needed.
– Hadi Brais
Mar 29 at 9:02
1
Good point. I looked at the manual of Supermicro X8DTN, which is a dual socket motherboard. The tables for optimal memory population shown on page 30 and 31 indicate that any of the two sockets can be populated or both. So yeah I think there needs to be some negotiation between the sockets (if there is more than one).
– Hadi Brais
Mar 29 at 9:31
1
@LewisKelsey Let's very carefully read how Section 8.4.3 of Volume 3 describes the BSP selection process. First, each processor is assigned a unique APIC ID (each logical core has a local APIC). Second, each logical processor is assigned an arbitration priority based on the APIC ID (which could be equal to the APIC ID). Third, each processor executes the built-in self test. Fourth, on modern Intel processors, each logical processor issues a NOP Special Cycle on the system bus. What does this mean?...
– Hadi Brais
Mar 29 at 19:13
1
...The Special Cycle is a type of transaction that is handled by the Ubox unit in the system agent as I'll describe shortly. In modern Intel processors, the system bus is basically the QPI interconnect. So putting it together, this means that each logical core issues a Special Cycle request to the Ubox and each such request is tagged with the arbitration priority of the logical core. The Ubox receives all of these requests (from the internal cores of the respective socket). Each Ubox chooses the request with the highest priority and then itself arbitrates for the QPI bus master lock...
– Hadi Brais
Mar 29 at 19:13
1
@LewisKelsey The Ubox is discussed in the Intel uncore manuals. The LIKWID documentation on the Ubox is actually from the manuals.
– Hadi Brais
Mar 31 at 17:25
|
show 12 more comments
I assume it's just hard-wired that one of the cores is the BSP. I don't think they other cores even power up until you send them an IPI, and they certainly wouldn't be running code that tries to take a mutex in cache to sort this out. The other cores probably come up in a HALT-like state that waits for an interrupt.
(But probably a deep sleep C-state like C7 or something, unlike the actual HALT instruction, so if the OS never wakes up some of the cores, putting the woken cores to sleep can let the whole package go into a deep sleep state.)
For multi-socket systems, presumably one socket is special somehow.
answered Mar 23 at 21:42
Peter CordesPeter Cordes
140k20214355
I assume it's just hard-wired that one of the cores is the BSP. I don't think they other cores even power up until you send them an IPI, and they certainly wouldn't be running code that tries to take a mutex in cache to sort this out. The other cores probably come up in a HALT-like state that waits for an interrupt.
(But probably a deep sleep C-state like C7 or something, unlike the actual HALT instruction, so if the OS never wakes up some of the cores, putting the woken cores to sleep can let the whole package go into a deep sleep state.)
For multi-socket systems, presumably one socket is special somehow.
answered Mar 23 at 21:42
Peter CordesPeter Cordes
140k20214355
answered Mar 23 at 21:42
Peter CordesPeter Cordes
140k20214355
answered Mar 23 at 21:42
Peter CordesPeter Cordes
140k20214355
answered Mar 23 at 21:42
Peter CordesPeter Cordes
140k20214355
140k20214355
1
I don't think hard-wiring the BSP works. My understanding is that we don't even know which of the physical cores will be working properly until after fabricating the chip (and marketing it as such). Otherwise, the hard-wired core might be the faulty one. So there is a need for a boot-time mechanism to choose one of the (properly working) logical cores as the BSP. I also don't understand the question. There can be many transactions on the ring or mesh at any point in time. I'm not sure why @LewisKelsey thinks that the arbitration ID is not needed.
– Hadi Brais
Mar 29 at 9:02
1
Good point. I looked at the manual of Supermicro X8DTN, which is a dual socket motherboard. The tables for optimal memory population shown on page 30 and 31 indicate that any of the two sockets can be populated or both. So yeah I think there needs to be some negotiation between the sockets (if there is more than one).
– Hadi Brais
Mar 29 at 9:31
1
@LewisKelsey Let's very carefully read how Section 8.4.3 of Volume 3 describes the BSP selection process. First, each processor is assigned a unique APIC ID (each logical core has a local APIC). Second, each logical processor is assigned an arbitration priority based on the APIC ID (which could be equal to the APIC ID). Third, each processor executes the built-in self test. Fourth, on modern Intel processors, each logical processor issues a NOP Special Cycle on the system bus. What does this mean?...
– Hadi Brais
Mar 29 at 19:13
1
...The Special Cycle is a type of transaction that is handled by the Ubox unit in the system agent as I'll describe shortly. In modern Intel processors, the system bus is basically the QPI interconnect. So putting it together, this means that each logical core issues a Special Cycle request to the Ubox and each such request is tagged with the arbitration priority of the logical core. The Ubox receives all of these requests (from the internal cores of the respective socket). Each Ubox chooses the request with the highest priority and then itself arbitrates for the QPI bus master lock...
– Hadi Brais
Mar 29 at 19:13
1
@LewisKelsey The Ubox is discussed in the Intel uncore manuals. The LIKWID documentation on the Ubox is actually from the manuals.
– Hadi Brais
Mar 31 at 17:25
|
show 12 more comments
1
I don't think hard-wiring the BSP works. My understanding is that we don't even know which of the physical cores will be working properly until after fabricating the chip (and marketing it as such). Otherwise, the hard-wired core might be the faulty one. So there is a need for a boot-time mechanism to choose one of the (properly working) logical cores as the BSP. I also don't understand the question. There can be many transactions on the ring or mesh at any point in time. I'm not sure why @LewisKelsey thinks that the arbitration ID is not needed.
– Hadi Brais
Mar 29 at 9:02
1
Good point. I looked at the manual of Supermicro X8DTN, which is a dual socket motherboard. The tables for optimal memory population shown on page 30 and 31 indicate that any of the two sockets can be populated or both. So yeah I think there needs to be some negotiation between the sockets (if there is more than one).
– Hadi Brais
Mar 29 at 9:31
1
@LewisKelsey Let's very carefully read how Section 8.4.3 of Volume 3 describes the BSP selection process. First, each processor is assigned a unique APIC ID (each logical core has a local APIC). Second, each logical processor is assigned an arbitration priority based on the APIC ID (which could be equal to the APIC ID). Third, each processor executes the built-in self test. Fourth, on modern Intel processors, each logical processor issues a NOP Special Cycle on the system bus. What does this mean?...
– Hadi Brais
Mar 29 at 19:13
1
...The Special Cycle is a type of transaction that is handled by the Ubox unit in the system agent as I'll describe shortly. In modern Intel processors, the system bus is basically the QPI interconnect. So putting it together, this means that each logical core issues a Special Cycle request to the Ubox and each such request is tagged with the arbitration priority of the logical core. The Ubox receives all of these requests (from the internal cores of the respective socket). Each Ubox chooses the request with the highest priority and then itself arbitrates for the QPI bus master lock...
– Hadi Brais
Mar 29 at 19:13
1
@LewisKelsey The Ubox is discussed in the Intel uncore manuals. The LIKWID documentation on the Ubox is actually from the manuals.
– Hadi Brais
Mar 31 at 17:25
1
1
I don't think hard-wiring the BSP works. My understanding is that we don't even know which of the physical cores will be working properly until after fabricating the chip (and marketing it as such). Otherwise, the hard-wired core might be the faulty one. So there is a need for a boot-time mechanism to choose one of the (properly working) logical cores as the BSP. I also don't understand the question. There can be many transactions on the ring or mesh at any point in time. I'm not sure why @LewisKelsey thinks that the arbitration ID is not needed.
– Hadi Brais
Mar 29 at 9:02
I don't think hard-wiring the BSP works. My understanding is that we don't even know which of the physical cores will be working properly until after fabricating the chip (and marketing it as such). Otherwise, the hard-wired core might be the faulty one. So there is a need for a boot-time mechanism to choose one of the (properly working) logical cores as the BSP. I also don't understand the question. There can be many transactions on the ring or mesh at any point in time. I'm not sure why @LewisKelsey thinks that the arbitration ID is not needed.
– Hadi Brais
Mar 29 at 9:02
1
1
Good point. I looked at the manual of Supermicro X8DTN, which is a dual socket motherboard. The tables for optimal memory population shown on page 30 and 31 indicate that any of the two sockets can be populated or both. So yeah I think there needs to be some negotiation between the sockets (if there is more than one).
– Hadi Brais
Mar 29 at 9:31
Good point. I looked at the manual of Supermicro X8DTN, which is a dual socket motherboard. The tables for optimal memory population shown on page 30 and 31 indicate that any of the two sockets can be populated or both. So yeah I think there needs to be some negotiation between the sockets (if there is more than one).
– Hadi Brais
Mar 29 at 9:31
1
1
@LewisKelsey Let's very carefully read how Section 8.4.3 of Volume 3 describes the BSP selection process. First, each processor is assigned a unique APIC ID (each logical core has a local APIC). Second, each logical processor is assigned an arbitration priority based on the APIC ID (which could be equal to the APIC ID). Third, each processor executes the built-in self test. Fourth, on modern Intel processors, each logical processor issues a NOP Special Cycle on the system bus. What does this mean?...
– Hadi Brais
Mar 29 at 19:13
@LewisKelsey Let's very carefully read how Section 8.4.3 of Volume 3 describes the BSP selection process. First, each processor is assigned a unique APIC ID (each logical core has a local APIC). Second, each logical processor is assigned an arbitration priority based on the APIC ID (which could be equal to the APIC ID). Third, each processor executes the built-in self test. Fourth, on modern Intel processors, each logical processor issues a NOP Special Cycle on the system bus. What does this mean?...
– Hadi Brais
Mar 29 at 19:13
1
1
...The Special Cycle is a type of transaction that is handled by the Ubox unit in the system agent as I'll describe shortly. In modern Intel processors, the system bus is basically the QPI interconnect. So putting it together, this means that each logical core issues a Special Cycle request to the Ubox and each such request is tagged with the arbitration priority of the logical core. The Ubox receives all of these requests (from the internal cores of the respective socket). Each Ubox chooses the request with the highest priority and then itself arbitrates for the QPI bus master lock...
– Hadi Brais
Mar 29 at 19:13
...The Special Cycle is a type of transaction that is handled by the Ubox unit in the system agent as I'll describe shortly. In modern Intel processors, the system bus is basically the QPI interconnect. So putting it together, this means that each logical core issues a Special Cycle request to the Ubox and each such request is tagged with the arbitration priority of the logical core. The Ubox receives all of these requests (from the internal cores of the respective socket). Each Ubox chooses the request with the highest priority and then itself arbitrates for the QPI bus master lock...
– Hadi Brais
Mar 29 at 19:13
1
1
@LewisKelsey The Ubox is discussed in the Intel uncore manuals. The LIKWID documentation on the Ubox is actually from the manuals.
– Hadi Brais
Mar 31 at 17:25
@LewisKelsey The Ubox is discussed in the Intel uncore manuals. The LIKWID documentation on the Ubox is actually from the manuals.
– Hadi Brais
Mar 31 at 17:25
|
show 12 more comments
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Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Sign up or log in
StackExchange.ready(function ()
StackExchange.helpers.onClickDraftSave('#login-link');
);
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Sign up using Google
Sign up using Facebook
Sign up using Email and Password
Post as a guest
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
Required, but never shown
