Styjun

Why does charmonium (and phi mesons) not decay via quark and antiquark annihilation?

What is the best option to connect old computer to modern TV

Benefits of employing devices that support vlan trunking

Why use water tanks from a retired Space Shuttle?

California: "For quality assurance, this phone call is being recorded"

Is there any Biblical Basis for 400 years of silence between Old and New Testament?

Do adult Russians normally hand-write Cyrillic as cursive or as block letters?

Will dual-learning in a glider make my GA learning safer?

PhD student with mental health issues and bad performance

Relativistic resistance transformation

Why is there a need to modify system call tables in Linux?

Is it legal in the UK for politicians to lie to the public for political gain?

How do you translate “is all” used at the end of a sentence?

Is American Express widely accepted in France?

If a problem only occurs randomly once in every N times on average, how many tests do I have to perform to be certain that it's now fixed?

Creating Fictional Slavic Place Names

Homophone fills the blanks

Rotated Position of Integers

Have powerful mythological heroes ever run away or been deeply afraid?

Are there mythical creatures in the world of Game of Thrones?

Applicants clearly not having the skills they advertise

How to detach yourself from a character you're going to kill?

Could a guilty Boris Johnson be used to cancel Brexit?

Client's editor wants to work directly on my InDesign files

How to fix positional associations Error (10437)

Multidimensional array problem in VHDL?Port Mapping memory components not workingDoes Quartus II support line.all?Data transfer between fpga (14 bits) vhdl block to NIos II system (16 bits)How do I combine incoming data and character in VHDL?Assigning Default Valuesgetting error for VHDL shift_left operationHow to implement a 4 bit ALU in VHDL using an opcodeWhy does this VHDL loop not terminate?How to create port map that maps a single signal to 1 bit of a std_logic_vector?

.everyoneloves__top-leaderboard:empty,.everyoneloves__mid-leaderboard:empty,.everyoneloves__bot-mid-leaderboard:empty height:90px;width:728px;box-sizing:border-box;

0

What I want to do is to take some bits of an std_logic_vector, then sign-extend them and afterwards assert them to another std_logic_vector

Lets say, I have the following

 A : std_logic_vector(31 downto 0);
 B : std_logic_vector(31 downto 0);

I want to do this:

A <= 000...0 & B(6 downto 0)
where "000...0" = 25 zeros

My Code is the following:

PC : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
PC_ADD : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

--- 
--- Inside the architecture i do this

PC_ADD <= (6 DOWNTO 0 => PC(8 DOWNTO 2), (OTHERS => '0'));

I get the following error:

Error (10437): VHDL Association List error at XXXXX.vhd: positional
associations must be listed before named associations

vhdl

share|improve this question

edited Mar 24 at 12:02

Broxigar

asked Mar 24 at 11:56

BroxigarBroxigar

45

• 
  
  
  

  
  

  
  
  
  
  
  

  
  
  You need to enable VHDL-2008 support. The parenthesis around others is wrong.
  
  – Paebbels
  Mar 24 at 17:22
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  
  Besides using --2008 remove the parentheses from around the second named association. Provide a minimal reproducible example. IEEE Std 1076-2008 9.3.3 Aggregates, 9.3.3.1 General, para 3 (in part) "An element association is said to be named if the elements are specified explicitly by choices; otherwise, it is said to be positional."
  
  – user1155120
  Mar 24 at 18:08
  
  

  
  
  
  

add a comment | 

0

What I want to do is to take some bits of an std_logic_vector, then sign-extend them and afterwards assert them to another std_logic_vector

Lets say, I have the following

 A : std_logic_vector(31 downto 0);
 B : std_logic_vector(31 downto 0);

I want to do this:

A <= 000...0 & B(6 downto 0)
where "000...0" = 25 zeros

My Code is the following:

PC : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
PC_ADD : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

--- 
--- Inside the architecture i do this

PC_ADD <= (6 DOWNTO 0 => PC(8 DOWNTO 2), (OTHERS => '0'));

I get the following error:

Error (10437): VHDL Association List error at XXXXX.vhd: positional
associations must be listed before named associations

vhdl

share|improve this question

edited Mar 24 at 12:02

Broxigar

asked Mar 24 at 11:56

BroxigarBroxigar

45

• 
  
  
  

  
  

  
  
  
  
  
  

  
  
  You need to enable VHDL-2008 support. The parenthesis around others is wrong.
  
  – Paebbels
  Mar 24 at 17:22
  
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  
  Besides using --2008 remove the parentheses from around the second named association. Provide a minimal reproducible example. IEEE Std 1076-2008 9.3.3 Aggregates, 9.3.3.1 General, para 3 (in part) "An element association is said to be named if the elements are specified explicitly by choices; otherwise, it is said to be positional."
  
  – user1155120
  Mar 24 at 18:08
  
  

  
  
  
  

add a comment | 

What I want to do is to take some bits of an std_logic_vector, then sign-extend them and afterwards assert them to another std_logic_vector

Lets say, I have the following

 A : std_logic_vector(31 downto 0);
 B : std_logic_vector(31 downto 0);

I want to do this:

A <= 000...0 & B(6 downto 0)
where "000...0" = 25 zeros

My Code is the following:

PC : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
PC_ADD : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

--- 
--- Inside the architecture i do this

PC_ADD <= (6 DOWNTO 0 => PC(8 DOWNTO 2), (OTHERS => '0'));

I get the following error:

Error (10437): VHDL Association List error at XXXXX.vhd: positional
associations must be listed before named associations

vhdl

share|improve this question

edited Mar 24 at 12:02

Broxigar

asked Mar 24 at 11:56

BroxigarBroxigar

45

 A : std_logic_vector(31 downto 0);
 B : std_logic_vector(31 downto 0);

A <= 000...0 & B(6 downto 0)
where "000...0" = 25 zeros

PC : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
PC_ADD : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

--- 
--- Inside the architecture i do this

PC_ADD <= (6 DOWNTO 0 => PC(8 DOWNTO 2), (OTHERS => '0'));

share|improve this question

edited Mar 24 at 12:02

Broxigar

asked Mar 24 at 11:56

BroxigarBroxigar

45

share|improve this question

edited Mar 24 at 12:02

Broxigar

asked Mar 24 at 11:56

BroxigarBroxigar

45

asked Mar 24 at 11:56

BroxigarBroxigar

45

asked Mar 24 at 11:56

BroxigarBroxigar

45